In certain electronic devices, it is often necessary to distribute a reference clock signal, or divisions thereof, to various digital circuitry in the devices. The reference clock may operate at high frequencies, such as, for example, above about 350 megahertz (MHz). However, such high frequencies may cause the digital circuitry to radiate signals as electromagnetic energy, and these electromagnetic emissions can interfere with the normal operation of surrounding equipment, a condition often referred to as electromagnetic interference (EMI). Since the electromagnetic emissions are based on the reference clock signal, emitted high energy “spikes” will be concentrated at the reference clock frequency and harmonics thereof.
In order to minimize EMI generated by such electronic devices, the electronic devices are often shielded, which adds significant bulk and cost to the devices and is therefore undesirable. Alternatively, the operation of the electronic devices may be modified so as to distribute the emitted energy over a wider frequency range, thereby reducing the energy emitted at any given frequency. One known methodology for modifying the operation of the electronic devices is to vary the clock frequency over a range of frequencies such that an average frequency is equal to the desired clock frequency, a technique known as “spread spectrum.” Phase-locked loops (PLLs) are well-suited for spread spectrum applications.
The PLL is a frequency-selective feedback system that is capable of synchronizing with a selected input signal and tracking frequency changes associated therewith. FIG. 1 illustrates a basic PLL 100 comprised of three functional blocks, namely, a phase detector 102, a loop filter 104, and a voltage-controlled oscillator (VCO) 106. These three blocks 102, 104, 106 are interconnected in a feedback arrangement as shown. The phase detector 102 compares the phase of a periodic input signal Vs(t) having a frequency fs with an output frequency of the VCO 106 and generates an error signal Vd(t). This error signal Vd(t) is then filtered by the loop filter 104 and is applied to a control input of the VCO 106 in the form of a filtered error signal Ve(t). The VCO 106 generates an output signal Vo(t) having a frequency which varies in response to the filtered error signal Ve(t).
When the VCO 106 is locked on the input signal, the VCO frequency is essentially identical to the frequency fs of the input signal Vs(t), except for a finite phase difference φo. This net phase difference φo is necessary to generate the corrective error voltage Ve(t) to shift the VCO from a free-running frequency f0 to fs to thereby maintain lock. The phase detector 102 generally functions as a mixer. The basic theory and principle of operation of PLLs are well known, as described, for example, in Alan B. Grebene, “Bipolar and MOS Analog Integrated Circuit Design,” pp. 627–678 (John Wiley & Sons 1984), which is incorporated herein by reference. Consequently, the theory and principle of operation of PLLs in general will not be presented in detail herein.
In a spread spectrum application, the PLL can be switched between a non-slewing mode, wherein the PLL maintains a substantially constant nominal frequency, and a frequency-slewing mode, wherein the PLL output frequency varies from a nominal value to a lower or higher value at which the PLL may be operated for a period of time. However, traditional PLLs are generally not capable of switching between modes in a smooth manner. Consequently, the PLL may undesirably generate glitches and/or may become unlocked during the transition between operating modes.
There exists a need, therefore, for an improved PLL that does not suffer from one or more of the problems exhibited by conventional PLL arrangements.